Global Wire Routing in Two - Dimensional Arrays 1

We examine the problem of routing wires of a VLSI chip, where the pins to be connected are arranged in a regular rectangular array. We obtain tight bounds for the worst-case "channel-width" needed to route an n x n array, and develop provably good heuristics for the general case. Single-turn routings are proved to be near-optimal in the worst-case. A central result of our paper is a "rounding algorithm" for obtaining integral approximations to solutions of linear equations. Given a matrix A and a real vector x, then we can find an integral i such that for all i, li~-x,l<l and (Ai)i-(Ax)i<A. Our error bound A is defined in terms of sign-segregated column sums of A: A=max(max(~ aij, ~-aisle.aided design for integrated circuits. 1. Problem Definition. We use a classical model of a gate-array wherein the chip area is considered to be divided into a uniform n x n array of square cells, Each cell contains p pins (connection points for logic elements). Each instance of our routing problem specifies a collection of nets where each net is specified as a set of pins. (Each pin is on at most one net.) Each net is to be connected together by horizontal and vertical wires. Unless stated otherwise, we assume that p = 1 and that each net connects exactly two pins. A placement (planar embedding) of the underlying circuit is implicit in an instance of the gate-array routing problem. The only remaining work is to route the wires between the pins. For this reason, the gate-array routing problem is a special case of (and perhaps easier than) the general placement and routing problem studied in [T], [L3], [L1], [L2], [BL], and [CR5]. It is common to solve a gate-array routing problem instance P in two steps: